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Renesas V850

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
  • Minimum instruction execution time: 31.25 ns (operating with main clock (fXX) of 32 MHz)
  • General-purpose registers: 32 bits × 32 registers
  • CPU features: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
  • Signed multiplication (32 × 32 → 64): 1 to 5 clocks
  • Saturated operations (overflow and underflow detection functions included)
  • 32-bit shift instruction: 1 clock
  • Bit manipulation instructions
  • Load/store instructions with long/short format
  • Memory space: 64 MB of linear address space (for programs and data)
  • External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
  • Non-maskable interrupts: 2 sources
    • Maskable interrupts: 60 sources
    • Software exceptions: 32 sources
    • Exception trap: 2 sources