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Home » PowerPC » e200
e200
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The e200 processor family is a set of CPU cores that implement low-cost versions of the Power Architecture™ Book E architecture. e200 processors are designed for deeply embedded control applications, which require low cost solutions rather than maximum performance.
The processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in some cases.
The e200z1 core is a single-issue, 32-bit Power Architecture Book E compliant design with 32-bit general purpose registers (GPRs). Power Architecture Book E floating-point instructions are not supported by e200 in hardware, but are trapped and may be emulated by software.All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs).
In addition to the base Power Architecture Book E instruction set support, the core also implements the VLE (variable-length encoding) APU, providing improved code density. The VLE APU is further documented in the PowerPC™ VLE APU Definition, Version 1.01, a separate document.
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