The e5500 core is a low-power implementation of the resources for embedded processors defined by the Power ISA™. The core is a 64-bit implementation and implements 32 64-bit general-purpose registers; however it supports accesses to 36-bit physical addresses.
The e5500 is a superscalar processor that can issue two instructions and complete two instructions per clock cycle. Instructions complete in order, but can execute out of order. Execution results are available to subsequent instructions through the rename buffers, but those results are recorded into architected registers in program order, maintaining a precise exception model.
The e5500 includes independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed L1 caches for instructions and data and a unified 512-Kbyte, eight-way set-associative, physically addressed, backside L2 cache.
