The e300 core is a low-power implementation of this family of reduced instruction set (RISC) microprocessors. The core implements the 32-bit portion of the PowerPC architecture, which defines 32-bit effective addresses, integer data types of 8, 16,32 bits, and floating-point data types of 32 and 64 bits. The core is a superscalar processor that can issues and retire as many as three instructions per clock cycle. Instructions can execute out of program order for increased performance, however, the core makes completion appear sequential.

Differences Between e300 Cores

The e300 core is the core used in Freescales family of PowerQUICC II Pro products and in some
PowerPC-based TSPG products. The e300 core was originally based on the 603e processor and
implements the classic PowerPC architecture. Several configurations of the e300 core exist, each with
different features. This is intended to be a very brief overview of differences between e300 cores. Please
consult the e300 Power Architecture Core Family Reference Manual for more in-depth information. Also
please note that some of this information is not to be made available to the public domain.

The following summerizes the differences between e300 cores.

Cache sizes - The e300c2 and e300c3 implement smaller L1 instruction and data caches for products with
lower power requirements.
Floating-point - The floating-point unit in the e300 core is the classic PowerPC 64-bit FPU
implementation. This means the e300 core supports 64-bit FPRs and supports all floating-point types in
hardware. Single- and double-precision operations are handled by this FPU in hardware. The e300c2 is the
only configuration that does not implement hardware support for floating-point operations. If
floating-point instructions are executed on the e300c2, an FPU unavailable exception (0x0800) is taken.
Integer units with enhanced multipliersMost configurations of the e300 core include two integer
execution units, which provide a higher throughput of integer operations. The increase in number of IUs
is transparent to software. The e300 configurations that include two integer units also include enhanced multipliers in each IU. The enhanced multipliers are faster than those of previous PowerPC
implementations, providing a maximum two-cycle latency for multiply instructions versus a maximum
six-cycle multiply instruction latency for previous PowerPC implementations.
Performance monitor - A performance monitor facility is included in some e300 configurations. This
provides the ability to count predefined events and processor clocks associated with particular operations,
such as cache misses, mispredicted branches, or the number of cycles an execution unit stalls.
Bus Interface - Most e300-based products implement a coherent system bus (CSB). Some e300 core
configurations, however, can optionally be integrated using a core complex bus (CCB), similar to that used
in e500-based products, instead of a CSB. The bus interface with which the e300 core is integrated is
product-specific and can be found in the SoC reference manual.
Frequency - Frequencies of e300 cores can be up to 667 MHz for the highest frequency parts. Frequencies
listed here are standalone core frequencies and are not necessarily frequencies that we disclose to
customers.
PVR - The core version number in the processor version register (PVR) is listed in this table, and the
revision level for each core starts at 0x0010 and changes for each revision of the core.

For more information consult "e300core Reference Manual'