The e500 processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processors that implement the Book E definition of the PowerPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words
in the 64-bit general-purpose registers (GPRs).

 Book E allows processors to provide auxiliary processing units (APUs), which are extensions to
the architecture that can perform computational or system management functions. One of these on
the e500 is the signal processing engine APU (SPE APU), which includes a suite of vector
instructions that use the upper and lower halves of the GPRs as a single two-element operand.
Most APUs implemented on the e500 are defined by the Freescale Semiconductor Book E
implementation standards (EIS).

 The e500 provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits, as defined
by Book E. It also provides two-element, 64-bit data types for the SPE APU and the embedded
vector floating-point APU, which include instructions that operate on operands comprised of two
32-bit elements.