 |
|
|
|
Home » Microchip PIC® » Microchip PIC24H
Microchip PIC24H Prozessoren 
|
Microchip PIC24H
|
The PIC24H Cpu has a 16-bit (data) modified Harvard architecture with an enhanced instruction set. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 24 bits wide and addresses up to 4M x 24 bits of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cyde, with the exception of instructions that change the program flow, the double-word move (Mov. D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point.
Registers
The PIC24H devices have sixteen, 16-bit working registers in the programmer’s model Each of the working registers can act as a data, address or address offset register. The 16th working register (Wi 5) operates as a Software Stack Pointer for interrupts and calls. The 15th working register (W14) can be used as a Stack Frame Pointer when used with LNI< and tJNLK instructions. The data space can be addressed as 32K words or 64 Kbytes.
The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word program boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The data to program space mapping feature lets any instruction access
program space as if it were data space. For more information on Program Space Visibility, refer to Section 4.4 “Program Space Visibility from Data Space”.
Addressing Modes
The CPU supports these addressing modes:
- Inherent (no operand)
- RelativeLiteralMemory
- Direct
- Register Direct
- Register Indirect
Each instruction is associated with a predefined Addressing mode group depending upon its functional requirements. As many as six Addressing modes are supported for each instruction. For most instructions, the PIC24H can execute these functions in a single instruction cycle.
- Data (or program data) memory read
- Working register (data) read
- Data memory write
- Program (instruction) memory read
As a result, three operand instructions can be supported allowing A + B = C operations to be
executed in a single cycle.
Arithmetic and Logic Unit
A high-speed, 17-bit by 17-bit multiplier is included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle:
The 16-bit Arithmetic Logic Unit (ALU) is enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete, but are interruptible at any cyde boundary.
Exception Processing
The PIC24H has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. |
|
|
|
|
|
|
|
|
|
| |
