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Home » Microchip PIC® » Microchip dsPIC33F
Microchip dsPIC33F Prozessoren 
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Microchip dsPIC33F
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The d5PIC33F CPU has a 16-bit (data) modified Harvard architecture with an enhanced
instruction set, including significant support for digital signal processing. The CPU has a 24-bit instruction word, with a variable length opcode field. The program counter (PC) is 24 bits wide and addresses up to 4M x 24 bits of user program memory space.
A single-cyde instruction pre-fetch mechanism helps maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (Mov . D) instruction and the table instructions. Overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
Registers
The dsPlC33F devices have sixteen 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address, or address offset register. The 16th working register (WI 5) operates as a software stack pointer for interrupts and calls.
Instruction Set
The dsPlC33F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many Addressing modes and was designed for optimum C compiler efficiency.
Data Space Addressing
The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and V data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operate solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP
instructions operate through the X and V AGUs to support dual operand reads, which splits the data address space into two parts. The X and V data space boundary is device specific.
The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data-space mapping feature lets any instruction access program space as it it were data space. Furthermore, RAM can be connected to the program memory bus on devices with an external bus and used to extend the internal data RAM.
Overhead-free circular buffers (modulo addressing) are supported in both X and V address spaces. The modulo addressing removes the software boundary-checking overhead for DSP algorithms. The X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit-reverse addressing to greatly simplify input or output data reordering for radix-2 FF1 algorithms.
Addressing Modes
The CPU supports these addressing modes:
- Inherent (no operand)
- Relative
- Literal
- Memory Direct
- Register Direct
- Register Indirect
Each instruction is associated with a predefined Addressing mode group, depending upon its
functional requirements. As many as six Addressing modes are supported for each instruction.
For most instructions, the dsPIC33F can execute these functions in a single instruction cycle:
- Data (or program data) memory read
- Working register (data) read
- Data memory write
- Program (instruction) memory read
As a result, three operand instructions can be supported, allowing A+B=C operations to be executed in a single cycle.
DSP Engine and Instructions
The DSP engine features:
- A high speed, 17-bit by 17-bit multiplier
- A 40-bit ALU
- Two 40-bit saturating accumulators
- A 40-bit bidirectional barrel shifter, capable of shifting a 40-bit value up to 16 bits right, or up to 16 bits left, in a single cycle
The DSP instructions operate seamlessly with all other instructions and are designed for optimal real-time performance. The r.ip~c instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers. This requires that the data space be split for these instructions and linear for all others. This is achieved in a transparent and flexible manner, through dedicating certain working registers to each address space.
Exception Processing
The dsPIC33F has a vectored exception scheme with up to eight sources of non-maskable traps and 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. |
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