TriCore® 1 is the first single-core 32-bit microcontroller-DSP architecture optimized for real-time embedded systems. TriCore® unifies the best of 3 worlds - real-time capabilities of microcontrollers, computational prowess of DSPs, and highest performance/price implementations of RISC loadstore architectures. The Instruction Set Architecture (ISA) supports a uniform, 32-bit address space, with optional virtual addressing and memory-mapped I/O. It allows for a wide range of implementations, ranging from simple scalar to superscalar. Furthermore, the ISA is capable of interacting with different system architectures, including those with multiprocessing. This flexibility at the implementation and system levels allows for different trade-offs between performance and cost at any point in time. To support TriCore® implementations with 32-bit instructions and simplified instruction fetching, the entire architecture is represented in 32-bit instruction formats. In addition, the architecture includes 16 bit instruction formats for the most frequently occurring instructions. These instructions significantly reduce code space, lowering memory requirements, system cost, and power consumption. Real-time responsiveness is largely determined by interrupt latency and context-switch time. The high-performance architecture minimizes interrupt latency by avoiding long multicycle instructions and by providing a flexible hardware-supported interrupt scheme. Furthermore, the architecture supports fast context switching.
Features Overview: