Provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
High-Speed 8051 μC Core
Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
20 vectored interrupt sources
Memory
4352 bytes internal data RAM (4 k + 256)
64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) Flash; in-system programmable in 512-byte sectors
External 64 kB data memory interface (programmable multiplexed or non-multiplexed modes)
Digital Peripherals
8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant Bosch Controller Area Network (CAN 2.0B), hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently
Programmable 16-bit counter/timer array with 6 capture/compare modules