This LSI is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Renesas Technology RISC (Reduced Instruction Set Computer) architecture with supporting functions required for an Ethernet system.

The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power. With this CPU, it has become possible to assemble low-cost, highperformance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcontrollers because of their high-speed processing requirements.

This LSI is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including cache memory, RAM, timers, a serial communication interface with FIFO (SCIF), host interface (HIF), interrupt controller (INTC), and I/O ports.

The external memory access support function of this LSI enables direct connection to various types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system cost.

Key Features:

• SH-2 (Renesas original SuperH 32-bit RISC)
• Mixed instructions/data cache (4kB)- 4-way set associative type
• Internal RAM (4 kB)
• Ethernet controller DMAC (EDMAC)- For transferring from EtherC receive FIFO to receive buffer x 1 channel- For transferring from transmit buffer to EtherC transmit FIFO x 1 channel-16 byte burst transfer
• Ethernet Controller (MAC *(Media Access Controller) 1
  • Conforming to IEEE802.3uCSMA/CD link management
• Data frame assembly/disassembly, CRC processing
• Conforms to the MII**(Media Independent Interface) standard, Magic PacketTM***
• Host Interface (HIF)- 1-kbytes x 2 banks:in total 2-kbyte buffer RAM- Interrupt requested to the external device- Internal interrupt requested to the CPU of this LSI- Booting from the buffer RAM is enabled if the external device has stored the instruction code in the buffer RAM
• Peripheral Functions- Ethernet Controller: 1 channel- Ethernet controller DMAC (EDMAC): 2 channels- Host Interface Function (1-kbyte x 2 banks)- Serial communication interface with FIFO (SCIF): 3 channels- Compare Match Timer: 2 channels- Watchdog timer: 1 channel- Clock pulse generator (CPG):On-chip clock-doubling PLL circuit- I/O Port
• Power Management Mechanism- Support for sleep/standby/module standby functions
  
  *: MAC: Media Access Controller
  **: MII: Media Independence Interface
  ***:Magic Packet is a registered trademark of AMD, Inc. in the United States.

Key Applications:

Digital audio-video equipment, Industrial equipment, Large household electrical appliances, Printers