The F280xx generation of devices offer 60-100Mhz performance. They feature an on-chip 12-bit ADC, multiple independent PWM and high resolution PWM peripherals as well as eQEP (quadrature encoder pins) and eCAP (event captures), up to 256KB flash memory in pin-compatible 100-pin packages. There are 12 members of the F280xx series and all of them are pin-to-pin compatible. RAM and ROM only versions are also offered. ROM versions are named with a “C” instead of an “F.”
Features:
High-Performance Static CMOS Technology
100 MHz (10-ns Cycle Time)
60 MHz (16.67-ns Cycle Time)
Low-Power (1.8-V Core, 3.3-V I/O) Design
JTAG Boundary Scan Support
High-Performance 32-Bit CPU (TMS320C28x)
16 x 16 and 32 x 32 MAC Operations
16 x 16 Dual MAC
Harvard Bus Architecture
Atomic Operations
Fast Interrupt Response and Processing
Unified Memory Programming Model
Code-Efficient (in C/C++ and Assembly)
On-Chip Memory
F2809: 128K X 16 Flash, 18K X 16 SARAM
F2808: 64K X 16 Flash, 18K X 16 SARAM
F2806: 32K X 16 Flash, 10K X 16 SARAM
F2802: 32K X 16 Flash, 6K X 16 SARAM
F2801: 16K X 16 Flash, 6K X 16 SARAM
F2801x: 16K X 16 Flash, 6K X 16 SARAM
1K x 16 OTP ROM (Flash Devices Only)
C2802: 32K X 16 ROM, 6K X 16 SARAM
C2801: 16K X 16 ROM, 6K X 16 SARAM
Boot ROM (4K x 16)
With Software Boot Modes (via SCI, SPI, CAN, I2C, and Parallel I/O)
Standard Math Tables
Clock and System Control
Dynamic PLL Ratio Changes Supported
On-Chip Oscillator
Watchdog Timer Module
Any GPIO A Pin Can Be Connected to One of the Three External Core Interrupts
Peripheral Interrupt Expansion (PIE) Block That Supports All 43 Peripheral Interrupts
