Developers can now deliver pixel-perfect images in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features an integrated image signal processing (ISP) solution and suite of peripherals saving developers on system costs. This ARM9-based DM365 device supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365. DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.
The DM365 processor core is an ARM926EJ-S RISC processor offering speeds up to 300MHz. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core incorporates:
- A coprocessor 15 (CP15) and protection module
- Data and program Memory Management Units (MMUs) with table look-aside buffers.
- Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
The DM365 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
- A Video Processing Front-End (VPFE)
- A Video Processing Back-End (VPBE)
The VPFE port provides an interface for ISIF/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support, SDTV/HDTV analog video and digital LCD output.
The DM365 peripheral set includes:
- An inter-integrated circuit (I2C) Bus interface
- One Multi-Channel Buffered Serial Port (McBSP)
- One Multi-Channel Buffered Serial Port (McBSP)
- Four 64-bit general-purpose timers each configurable as two independent 32-bit timers
- A 64-bit watchdog timer
- Up to 104 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
- Two UARTs with hardware handshaking support on one UART
- Five serial port Interfaces (SPI)
- Four pulse width modulator (PWM) peripherals
- Four real time out (RTO) outputs
- Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
- Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
- A USB 2.0 full and high-speed device and host interface
- Six channel Analog to Digital Convertor (ADC)
- Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NOR flash, SRAM, NAND, and OneNAND
- A high speed synchronous memory interface for DDR2/mDDR.
- Power Management and Real Time Clock Subsystem (PRTCSS)
- HPI
- EMAC
- Key Scan
- Voice Codec
For software development support the DM365 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
- High-Performance Digital Media System-on-Chip (DMSoC)
- 270-, 300-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9™
- ARM926EJ-S™ Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT Logic for Real-Time Debug
- ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 16K-Byte ROM
- Little Endian
- Two Video Image Co-processors (HDVICP, MJCP) Engines
- Support a Range of Encode and Decode Operations
- H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
- Video Processing Subsystem
- Front End Provides:
- Hardware IPIPE for Real-Time Image Processing
- Resize Engine
- Resize Images From 1/16× to 8×
- Separate Horizontal/Vertical Control
- Two Simultaneous Output Paths
- IPIPE Interface (IPIPEIF)
- Image Sensor Interface (ISIF) and CMOS Imager Interface
- 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
- Glueless Interface to Common Video Decoders
- BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
- Histogram Module
- Lens distortion correction module (LDC)
- Hardware 3A statistics collection module (H3A)
- Back End Provides:
- Hardware On-Screen Display (OSD)
- Composite NTSC/PAL video encoder output
- 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
- 3 DACs for HD Analog Video Output
- LCD Controller
- BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
- Analog-to-Digital Convertor (ADC)
- Power Management and Real Time Clock Subsystem (PRTCSS)
- 16-Bit Host-Port Interface (HPI)
- 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
- Key Scan
- Voice Codec
- External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
- Flash Memory Interfaces
- NAND (8-/16-bit Wide Data)
- 16 MB NOR Flash, SRAM
- OneNAND(16-bit Wide Data)
- Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia/xD
- Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
- USB port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 High-Speed Device
- USB 2.0 High-Speed Host (mini-host, supporting one external device)
- USB On The Go (HS-USB OTG)
- Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
- One 64-Bit Watch Dog Timer
- Two UARTs (One fast UART with RTS and CTS Flow Control)
- Five Serial Port Interfaces (SPI) each with two Chip-Selects
- One Master/Slave Inter-Integrated Circuit (I2C) Bus™
- One Multi-Channel Buffered Serial Port (McBSP)
- I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Direct Interface to T1/E1 Framers
- Time Division Multiplexed Mode (TDM)
- 128 Channel Mode
- Four Pulse Width Modulator (PWM) Outputs
- Four RTO (Real Time Out) Outputs
- Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
- Boot Modes
- On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
- AEMIF (NOR and OneNAND)
- Configurable Power-Saving Modes
- Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
- Flexible PLL Clock Generators
- Debug Interface Support
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
- 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
- 65nm Process Technology
- 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
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