Product Overview:

This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology original architecture as its core, and the peripheral functions required to configure a system, eg PC server.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.
This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit free running timer (FRT), an 8-bit timer(TMR), a watchdog timer (WDT), a serial communication interface (SCI), an I2 C bus interface (IIC), an LPC interface (LPC), a D/A converter, an A/D converter, and I/O ports as on-chip peripheral modules required for systemconfiguration.
A data transfer controller (DTC) is included as a bus master.
A flash memory version is available for this LSI in 256, 384, and 512-kbyte ROM. The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This improves the instruction fetch and process speeds.
Two operating modes are provided, offering a choice of address space and single chip mode/external extended mode. Boot programming into a flash memory, on-chip emulation, and boundary scan can be selected as special operating modes.

Key Features:

• Operating frequency (MHz)/Supply voltage (V)
  • 33MHz/3.0 to 3.6V
• On-chip memory
  • ROM: 256kB/384kB/512kB Flash
  • RAM: 40 kB
• Bus Controller
  • Normal bus or multiplexed bus interface
• LPC: I/O Read/Write 3ch
  • Programmable 16 bit address
  • 64 byte block transfer transmit and receive buffers
• SCI: 3ch
  • Smart Card I/F Support
• IIC: 6ch
  • Multi-master/slave function
  • Implements I2C bus extended control register (ICXR)
• Timer
  • 16 bit free running timer x 1ch
  • 8 bit timer x 4ch (Operation as a 16-bit timer can be performed using TMR_0and TMR_1)
  • Watch-dog timer x 2ch
• PWM: 14bit x 4ch
  • Use Fun control
  • Lowest PWM output frequency is 7.9Hz @ 33MHz
  • Each channel can be used a different clock input
• CRC
  • Choice 3 polynomial (X8+X2+X+1, X16+X15 +X2+1, X16+X12+X5+1)
• User debug interface: JTAG interface
• Package: PackageCodeBody sizePin pitchTQFP-144 TFP-144
  (PTQP0144LC-A) 10.0×10.0mm0.8mm

Key Applications:

Office automation equipment

Built-in Functions

• High-speed H8S/2000 central processing unit with 16-bit architecture
  • Upward-compatible with H8/300 and H8/300H CPUs on an object level
  • Sixteen 16-bit general registers
  • 65 basic instructions
  • Address space: 16M byte
• Interrupt
  • Internal: 48
  • External: 17
• Bus controller
  • External data bus width: 8/16 bits
• Varioius peripheral functions
  • Data transfer controller (DTC) x 85ch
  • 8-bit PWM timer (PWM) x 16ch
  • 14-bit PWM timer (PWMX) x 4ch
  • 16-bit free-running timer (FRT)
  • 8-bit timer (TMR) x 4ch
  • Watchdog timer (WDT) x 2ch
  • Asynchronous or clocked synchronous serial communication interface (SCI) x 3ch
  • CRC operation circuit (CRC)
  • I2C bus interface (IIC) x 6ch
  • LPC interface (LPC) x 3ch
  • 10-bit A/D converter x 8ch
  • 8-bit D/A converter x 2ch
  • Boundary scan (JTAG)
  • Clock pulse generator
• General I/O ports
  • I/O pins: 106
  • Input-only pins: 9