• ±1 LSB INL (C8051F52x/C8051F53x); no missing codes
• Programmable throughput up to 200 ksps
• Up to 6/16 external inputs
• Data dependent windowed interrupt generator
• Built-in temperature sensor

• Programmable hysteresis and response time
• Configurable as wake-up or reset source
• Low current

• On-chip debug circuitry facilitates full-speed, non-intrusive in-system debug (No emulator required)
• Provides breakpoints, single stepping
• Inspect/modify memory and registers
• Complete development kit

• Built-in LDO regulator

• Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
• Up to 25 MIPS throughput with
• 25 MHz system clock
• Expanded interrupt handler

• 8/4/2 kB Flash; In-system byte programmable in 512 byte sectors
• 256 bytes internal data RAM

• 16/6 port I/O; push-pull or open-drain, 5 V tolerant
• Hardware SPI™, and UART serial port
• Hardware LIN (both master and slave, compatible with V1.3 and V2.0)
• Three general purpose 16-bit counter/timers
• Programmable 16-bit counter/timer array with three capture/compare modules, WDT

• Internal oscillators: 24.5 MHz ±0.5% accuracy supports
• UART and LIN-Master operation
• External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
• Can switch between clock sources on-the-fly

• 10-Pin QFN (3 x 3 mm)
• 20-pin QFN (4 x 4 mm)
• 20-pin TSSOP

Datenblatt